Tiny Encryption Algorithm Tea Computer Science Essay

lilliputian encoding Algorithm Tea run intor Science EssayToday, warrantor is an issue concern by everyone. umteen ways of implementing figureion algorithmic rules have been investigated in couch to achieve improve performance in terms of security level, speed, power consumption and cost. This task pass on discuss about implementing Tiny encoding Algorithm ( afternoon tea) utilize Field Programmable Gate Array (FPGA). FPGA argon reconfigurable chips that the integrated turn is intentional meant for reconfigurable architecture. A FPGA chips is programmed using Hardwargon Description Language (HDL). tea is an encoding algorithm or mental head off suppose that consider fast, easy and utilize for many application. In this fuddle, tea leave be utilise on Altera Cyclone II FPGA using Altera DE1 Board. Key control board using PS2 or the SWITCH on the DE1 leave behind be dropd as input. The output of the encryption and decoding selective information forgeting be show on VGA monitor. The encrypted information exit be store in retention.Specific ObjectivesIn order to complete this project, in that location argon few objectives have to be archieve.Program the Tiny encoding Algorithm (TEA) using verilog HDL ( ironw be Description Language)Verifying the functionality of the murder of the encryption in FPGAPerform cloak for clock analysis and the encryption wait on on the slaying of Tiny encoding Algorithm (TEA) in FPGA audition and test the project in practicalLiterature Research cryptanalyticsBefore the modern era, security conversation is the primary concern in Government and Military2. Security communication fail to a greater extent important directly as a result of the increase use of the electronic communication for many daily activities much(prenominal) as internet banking, online shopping. Cryptography is a practical way of conveying information securely 1. The main strike of cryptography is to solelyow authorized person t o receive the message mighty while preventing eavesdroppers understanding the content of the message 1. The original message is called plaintext t1. Plaintext will be encrypted using certain algorithms in the secure carcass in order to hide the meaning1. The output of this rechargeable mathematical subprogram is called naughttext and the algorithm used in this process is called elaborate 1. thinktext quite a little be transmitted securely because ideally eavesdroppers that access to the ciphertext wont understand what the meaning is fag oddment 1. The reverse of this mathematical process is to decrypt the ciphertext back to plaintext and this only hindquarters be done by the original recipients 1. The processes of encryption and decipherment are shown in stick out 1.EavesdropperPlaintextencryptionCiphertextPlaintextDecryption sort 1EncryptionThere are cardinal founts of encryption or cipher depends on the find used Asymmetric get a line and centrosymmetric separ ate. even place fruit The encryption and decryption process use the resembling key 1. The major worrys and drawback of this key both sender and receiver mustiness know the key prior to the transmissions 1. If the key is transmitted then it will compromise the schemes security 1. The advantages of symmetric key is the process of encryption and decryption will be meteoric compare to asymmetric key, in an new(prenominal) words it jakes encrypt or decrypt more information in shorter stay of time 1.Asymmetric key The encryption and decryption process use different key roughly both of the key are think mathematically 1. It is very hard to obtain one from the other although they are mathematically related 1. The public key is used for the encryption process and the private key is used for the decryption process 1. The security of the system wont be compromised even though the public key is do available but the corresponding private key cannot be revealed to anyone 1.Symm etric keySymmetric key is further divided into two lawsuits Symmetric Cipher and sidestep Cipher. bourgeon Cipher Stream cipher that generates a keystream (a sequence of insect bites used as a key) 4. The encryption process is unremarkably done by combining the keystream with plaintext using bitwise XOR operation 4. Keystream that generated is independent of the plaintext and ciphertext is called co-occurrent stream cipher while keystream that is generated is depent of plaintext is called self-synchronizing stream cipher 4.Block Cipher Stream cipher that generates a keystream encrypt fixed length block of plaintext into block ciphertext that is equal length 3. The fix length is called block size. Block Cipher using same secret key for the encryption and decryption process 3. Usually, the size of block cipher is 64 bits 3. By increasing the size of block cipher to 128 bits will make the mainframe computers become more sophisticated 3.Stream Cipher vs Block CipherStream ciphe r is a fibre of symmetric encryption algorithm that can be intentional to be exceptionally fast and even much faster compare to block cipher 4. Stream ciphers normally process on less bits while block ciphers can process large blocks of data 4. Plaintext that encrypted using block cipher will result in the same ciphertext when the same key is used 4. With a stream cipher, the transformation of thse small plaintext units will vary depending on when they are encountered during the encryption process 4.Stream CipherBlock CipherBlock SizeDependsFixedEncryption/Decryption SpeedFastSlowerSize of block data can be processSmallLarger issue 2 Comparison of Stream Cipher and Block CipherFigure 3 infra shows different type of algorithmtable.jpgFigure 3 Different type of encryption algorithmTiny Encryption Algorithm is implemented in this project because it is one type of cipher encryption algorithm that encrypt 64 bits of plaintext using a 128 bits of key into a 64 bits ciphertext.TEATiny Encryption Algorithm (TEA) is a Feistel type routine designed by David J. Wheeler and Roger M. Needham. It used addition and subtraction as the reversible operators 5. XOR and ADD alternately used in the routine provide nonlinearity 5. The double bit shifting in the routine cause all the bits and data mixed repeatedly 5. The three XOR, ADD and SHIFT operation will provide Shannons properties of diffusion and confusion necessary for a secure block cipher without the need for P-boxes and S-boxes 6. TEA is a feistel cipher that split the plaintext into halves 7. A sub key will be applied to the one half of plaintext in the cycle per second function, F 8. Then the output of the F will be XOR with other half before the two halves are swapped 8. in all same patterns applied to the entire round except the last round where there is often no swap 8. Figure 2 below show a Feistel cipher diagram where 64 bits of plaintext is divided into halves which are equally 32 bits each part. 128 bits of key is used for the encryption and decryption process and it is spitted into 32 bits subkey 7.TEA.pngFigure 4 Two Fiestal round(one cycle) of TEAThe encryption and decryption routine of Tiny Encryption Algorithm (TEA) written in C talking to 5.void encrypt (uint32_t* v, uint32_t* k, uint32_t* v1) uint32_t v0=v0, sum=0, i /* furbish up up */uint32_t delta=0x9e3779b9 /* a key roll constant */uint32_t k0=k0, k1=k1, k2=k2, k3=k3 /* cache key */for (i=0 i sum += deltav0 += ((v15) + k1)v1 += ((v05) + k3) /* end cycle */v0=v0 v1=v1void decrypt (uint32_t* v, uint32_t* k, uint32_t* v1) uint32_t v0=v0, sum=0xC6EF3720, i /* set up */uint32_t delta=0x9e3779b9 /* a key schedule constant */uint32_t k0=k0, k1=k1, k2=k2, k3=k3 /* cache key */for (i=0 iv1 -= ((v05) + k3)v0 -= ((v15) + k1)sum -= delta /* end cycle */v0=v0 v1=v15delta is derived from the golden number wheredelta =ArchitecturesUntitled.jpgFigure 5 TEA architecturesTEA is implemented using three different architectures. The first architecture (Figure 3a) is a multiple 32 bit adders that simultaneously perform operations necessitate for one encryption cycle 6. This parallel form structure should be quite large in terms of computer computer hardware discipline but will perform faster 6. On the other hands, in order to reduce the area, the second architecture (Figure 3b) performs operations sequentially using a iodine 32 bit adder 6. The last design (Figure 3c) is a 8 bit digit- serial adders that use advance architecture offered by application-specific hardware solution 6. The latter two design are meant for low area solutions but in terms of control and data selection, the effectiveness catch ones breath confirmed 6.Software vs Hardware executing of EncryptionImplementation of encryption using software is easier to design and upgrade, it besides portable and flexible 7. wizard of the major problems of software implementation is in most typical individual(prenominal) computer have external memory ou t from the processor, the external memory is used to store raw data or breeding in unencrypted form so if an attacker gain access to the system, the key can be easier obtained 7. One of the most common way used by the attacker is bruteforce, a special program can be considerably design to bruteforce the algorithm. Besides this, reverse engineering method easier to apply on software implementation. So it can be concluded that software implementation is lack of physical security7.Implementation of encryption using hardware by naturally is physically more secure as they are hard to read and view by attacker 7. Another advantage of hardware implementation is all the data in the encryption process is cor congress according to an algorithm which usually perform operation on same data 7. This will prevent computer technique such as out of order execution and cause hang to the system 7. Hardware implementation also tend to be more parallel so more orders of magnitudes can be done at cert ain bound of time 7.Hardware implementation is will be part pickax for encryption in terms of performance but the cost of implementation is higher compare to software implementation. Higher security level and smash performance is the main concern in this project, so the encryption will be implemented on FPGA, one of the hardware implementation method.Microcontroller, Microprocessor, DSP processor and FPGAMicroprocessorThe first microprocessors invented in the 1970s 10. This is the first time where such an frightening devices put a computer processor onto a single IC 10. The significant processing was available at rather low cost, in comparatively small space 10. At beginning stage, all other functions, like input/output interfacing and memory were outside the microprocessor 10. Gradually all the other functions in embedded into a single chip 10. At the same time, microprocessor becoming more powerful in terms on the speed, power consumption and so on 10. Microprocessor is mov ing rapidly from 8 bits to 32 bits 10.MicrocontrollerA microcontroller is an inexpensive single-chip computer 9. The entire computer system lies within the confines of the integrated term of enlistment chip, so it is called a single chip computer 9. The microcontroller on the encapsulated sliver of silicon has features analogous to those person-to-person computers 9. Mainly, the microcontroller is able to store and run a program 9. The microcontroller contains a CPU (central processing unit), ROM (random-access memory), RAM (random-access memory), Input/Output lines, and oscillator, serial and parallel ports 9. Some more advanced microcontroller also have other reinforced in peripherals such as A/D (analog-to-digital) converter 9.DSP (Digital manoeuvre Processing) ProcessorDSP processor is a specialized microprocessor optimized to process digital call for 1213. Most of the DSP processors are commonly designed to have basic features such as high performance, repetitive and numer ically intensive tasks so DSP processor often have advantage in terms of speed, cost and cypher efficiency 11. DSP processor have the avility to perform one or more multiply accumulate operations (often called MACs) in a single instruction cycle 14.FPGA (Field Programmable Gate Array)Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the first commercially viable line of merchandise programmable gate array in 1985 the XC2064. FPGA is integrated circuit for reconfigurable purposes by user after manufacturer. FPGA is generally specified using Hardware Description language (HDL). FPGA can be programmed to perform logic function and due to this ability, FPGA become more popular. Using FPGA for design can lower non recurring plan cost and apply on many application.Hardware Architectures comparisonThe figure 6 below show the comparison of different architectures used for hardware implementation on encryption.ArchitectureEfficiencyPerformanceNon recurring engineer C ostUnit CostMicroprocessor slumpLowLowLowMicrocontrollerLowLowLowLowDSP processor take holdModerateLowModerateFPGAHighHighLowHighFigure 6 Architectures ComparisonComparing the four architectures above, FPGA have the advantage in terms of the efficiency Performance but the unit cost is high. Since cost is not a major concern in this project, so FPGA is better choice for implementing Tiny Encryption Algorithm.Altera DE1 Development and Education BoardAltera DE1 is a FPGA Development and Education Board that will be used for this project 17. Below is the features of this boardDE1_intro_500x.pngFigure 7 Altera DE1 BoardAltera Cyclone II 2C20 FPGA with 20000 LEsAltera ordered Configuration deivices (EPCS4) for Cyclone II 2C20USB Blaster built in on board for programming and user API controllingJTAG Mode and AS Mode are supported8Mbyte (1M x 4 x 16) SDRAM4Mbyte Flash stock512Kbyte(256Kx16) SRAMSD greenback Socket4 Push- clitoris overcomees10 DPDT switches8 Green User LEDs10 red ink U ser LEDs4 Seven-segment LED displays50MHz oscillator ,24MHz oscillator ,27MHz oscillator and external clock sources24-bit CD-Quality Audio CODEC with line-in, line-out, and microphone-in jacksVGA DAC (4-bit R-2R per channel) with VGA out connectionRS-232 Transceiver and 9-pin linkPS/2 mouse/keyboard connectorTwo 40-pin Expansion HeadersDE1 Lab CD-ROM which contains many examples with source recruitSize153*153 mmThere are few features of DE1 Board will be used for this project.PS/2 mouse/keyboard connectorPS/2 keyboard is used as input for the plaintext4 Push button switchesused as a determine buttonVGA DAC (4-bit R-2R per channel) with VGA out connectorVGA monitor is connected to the DE1 board to show the input of plaintext and the output of the encryption, cipher text4Mbyte Flash MemoryUsed to store the ciphertextVGA controllerIBM hive away video display standard called VGA (video graphics array) in the late eighties that widely supported by PC graphics hardware and monitors 18.Figure 8 Simplified Block Diagram of VGA ControllerThe vga_sync circuit generates timing and synchronization signals 18. The hsync and vsync signals are connected to the VGA port to control the horizontal and unsloped scans of the monitor 18. Two signals which are pel_x and pixel_y are de autographd from the internal counters 18. The pixel_x and pixel_y signals indicate the relative positions of the scans and essentially specify the location of the current pixel 18. Videl_on signal is generated from vga_sync to survey whether the display is enable or disable 18. The pixel generation circuit generate three video signal which is RGB signal 18. The current coordinates of the pixel (pixel_x and pixel_y), external control and data signals moderate the color value 18.PS/2 ControllerIBM introduced PS2 port in personal computers 18. It is a widely used interface for keyboard and mouse to communicate with the host 18. PS2 port consists of two wires for communication purposes 18. One w ire for transmitting data in serial stream while another wire is for the clock information which determine when the data is valid and can be retrieved 18. The data is transmitted in 11 bit packet that contains 8 bits of data, an odd parity bit and stop bit 18.Figure 9 Timing Diagram of a PS/2 portQuartus II Web EditionQuartus II Web Edition design software is a comprehensive surroundings available for system-on-a-programmable-chip (SOPC) design developed by Altera 19. This software is used in this project to program and implement the Tiny Encryption Algorithm (TEA) on Altera DE1 Cyclone II FPGA 19. This program also can be used for the simulation and timing analysis 19.Hardware Description Language (HDL)Hard explanation language (HDL) is a type of programming languages used to program and unwrap digital logic or electronic circuits 20. It can describe circuit operation, its design and organization 20. Figure 10 below shows different type of Hardware Description Language commonly used.HDLSyntax similitudeAHDLAda programming LanguageVHDLAda Programming LanguageJHDL javaVerilogC Programming LanguageFigure 10 Different type of HDLVerilog Hardware Description Language (HDL) is used to program the FPGA in this project because it is a widely used HDL and it syntax is similar the C programming language.MethodologyBlock DiagramVGA MonitorPS/2 KeyboardVGA ControllerPlaintextTEA Encryption CoreFlash Memory64 BitsCiphertextPS/2 ControllerKey128 Bits64 BitsEncryption/DecryptionAcknowledgeKey modify RequestBusyasynchronous ResetClockFigure 11 Core ModuleThe blog Diagram above explains the design of this project. PS/2 keyboard used as input for the plaintext. All the data from the PS/2 keyboard will be sent into PS/2 controller to process. The processed data, 128 Bits or key or 64 Bits of plaintext will sent into the TEA encryption meaning for encryption. The output of the encryption, ciphertext will store inside the flash memory. All the plaintext and cipher text wil l send into VGA controller to process and show on the cathode-ray tube monitor. The encryption/decryption will be connected to the DPDT switch to switch between encryption or decryption mode. Key Update Request also connected to the DPDT switch for the purpose of updating the key when the switch is on. Asynchronous reset is connected to the push button for the reset purpose. There are internal clock inside the DE1 board so no external clock is needed for this project.Algorithm and Implementation haltThe original Tiny Encryption Algorithm C source code by the author will be compiled or get a compiled executable program from other source to analyze the encryption of plaintext to ciphertext and decryption of ciphertext back to plaintext. A set of plaintext, ciphertext and key can generated from the program as a reference and compare with the encryption and decryption output implemented on FPGA.Figure 12 is an example of compiled executable program of Tiny Encryption Algorithm by Andre as JonssonTEA.jpgFigure 12Costing unionComponentsQuantityPriceAltera De1 Board 171RM 512.84Used 15 Samsung SyncMaster CRT monitor1RM50.00Used PS/2 Keyboard1RM10.00 fareRM572.84Gantt Chartganchart.jpgResearch analysis will be start from calendar week 6 till week 8. Verilog coding on the implementation of TEA and module and test bench verification this 2 task must perform parallel because after swallow up a certain module, it should be test and simulate. If simulation or test is done after finish the whole coding, there will be a big problem in debugging the error. The synthesis of PS/2 keyboard, VGA monitor and FPGA start week 20 just before finish the coding. The functionality verification task also runs parallel with the synthesis optimization task.References and FiguresFiguresFigure 4 Tiny Encryption Algorithm .Available athttp//en.wikipedia.org/wiki/Tiny_Encryption_Algorithm (Accessed 30 October 2009)Figure 5 Israsena. P, Design and Implementation of Low Power Hardware Encryp tion for Low Cost sterilise RFID Using TEA . Information, Communications and Signal Processing, 2005 Fifth International assemblage on 0-0 0 Page(s)1402 1406, DOI 10.1109/ICICS.2005.1689288. Available athttp//ieeexplore.ieee.org/stamp/stamp.jsp?tp=arnumber=1689288isnumber=35625 (Accessed 26 October 2009)Figure 7 Available athttp//www.terasic.com.tw/cgi-bin/page/archive.pl?Language=EnglishNo=83( Accessed 28 October 2009)Figure 8 Pong P. Chu (2008) FPGA Prototyping by Verilog Examples John Wiley SonsFigure 9 Pong P. Chu (2008) FPGA Prototyping by Verilog Examples John Wiley Sons